8259 PIC ( Programmable Interrupt Controller )

8259 PIC abbreviated as programmable interrupt controller, In the previous tutorial an overview of it was given. In this tutorial 8259 Architecture, working and 8259 pin diagram. To access complete series of 8086 click here.

• It is used to increase the number of interrupts.
• This was designed by INTEL and for 8085 and 8086.
• Single it would provide 8 interrupts and a maximum of 64 interrupts can be provided using the concept of cascading.
• It has a flexible priority order for interrupts, By default there is a priority order which can be changed by giving commands to 8259 PIC.
• Both the interrupts ( edge and level interrupts ) can be handled by 8259 PIC.
• It should be initialized to set properties like priority order, masking( masking an interrupt means ignoring/excluding the interrupt) , vector numbers, triggering.

There are two interrupt pins to 8086 microprocessor ( NMI and INTR ), NMI is vectored interrupt , whereas INTR is non-vectored interrupt , It is attached to INTR of 8086 microprocessor.

8259 PIC Working

1. Interrupt is received by 8259 PIC through 8-IR pins [ IR0>IR1…..>IR7 (default priority order) ]. This priority order can be changed while initialization. 
2. Most prior interrupt is sent to 8086 by INTR pin.
3. Once 8086 receives interrupt , 8086 sends interrupt acknowledgement( using INTA bar ), 8086 sends to two low pulses by INTA bar pin.
   In the first low pulse it determines vector number
   In the second low pulse it sends vector number to 8086
   These two pulses are required because PIC is connected to non-vectored interrupt.
4. Here data bus is bidirectional, PIC sends vector number and receives commands for initialization ( priority order, trigger, masking….. )

8259 Architecture

There are three 8-bit registers in 8259 PIC as follows

• In service Register ( InSR/ISR )
• Interrupt Mask Register ( IMR )
• Interrupt Request Register ( IRR )

Firstly the block on the top left is the data bus buffer , which connects a bidirectional data bus. This 8-bit data bus is used to send vector numbers to 8086 and used to receive commands while initialization.  If there is a data bus, then there should be read and write logic too, which would be given by an 8086 microprocessor. A₀ and CS bar ( chip set ), these pins are not used in this case. The third block ( cascade buffer comparator ), is used while cascading 8259 PICs. 

When interrupts occur in 8259 PIC ( 8 interrupts can be occurred at a time ), whichever the interrupt occurs, respective bit in IRR is set to high.
If any interrupt is masked ( this is set to IMR while initialization, by default all bits of IMR are 0 ). If the masked interrupt is occured, then that interrupt is neglected.
For the non-masked interrupts, priority resolver gives the priority ( by default priority is highest to IR0 and lowest to IR7 ). And at last the most prior interrupt is sent to 8086 microprocessor to get serviced. The interrupt which is being serviced is set in InSR. 

For Instance: In 8259 PIC

In InSR IR1 is 1, which means currently Interrupt 1 is being serviced. At this moment IR2, IR4 and IR7 has occurred simultaneously. Priority resolver block takes input from all three registers and gives the priority.

• Interrupt 2 is masked.
• IR2, IR4 and IR7 are considered at starting, but IR2 is ignored as it is masked. So IR4 and IR7 are left with IR4 as higher priority.
• IR1 is currently serviced and IR4, IR7 are in queue. If IR0 has occurred , then IR1 would be paused and IR0 would be serviced first due to higher priority.
• Priority resolver doesn’t give priority only to pending interrupts but also includes the in-service interrupt also.  

8259 Pin Diagram

• Pin no 17 to 25 are the interrupt pins
• Pin no 4 to 11 are 8-bit bidirectional data bus
• Pin no 2,3 are write and read respectively. 
• Check out the architecture part, to know about all pins. 

For extra information visit wikipedia page.