control signals
micro operations
logic micro operations
micro operations in computer architecture
Micro-operation & control signal
- A Program is a set of Instructions.
- An Instruction requires a set of small operations called Micro-Operations.
- A Micro-Operation is a finite activity performed by the processor in one clock cycle. One clock
- The cycle is also called one T-state (Transition state).
- One Micro-Operation requires One T-state.
- Several Independent Micro-Operations can be performed in the same T-state.
- Control unit generates control signals to perform these very Micro-Operations.
- To understand Control Units, we must first clearly understand Micro-Operations.
Micro-operation for instruction fetching
| STATE | MICRO-OPERATION | EXPLANATION . |
| T1 | MAR ←PC | PC puts address of the next instruction into MAR |
| T2 | MBR ←Memory | MBR gets instruction from memory through data bus |
| T3 | IR ←MBR PC←PC +1 | IR gets instruction from MBRPC gets incremented |
Two micro-operations are possible, as seen in the table above.
IR€ MBR and PC€ PC + 1 are in the same T condition.
This is due to the fact that they are wholly independent of one another.In reality, while the instruction is being executed, PC can also become PC + 1 in the 2nd T-state retrieved into MBR through the data bus from the memory.
Micro-operation for instruction fetching(Alternate method):
| STATE | MICRO-OPERATION | EXPLANATION . |
| T1 | MAR ← PC | PC puts address of the next instruction into MAR |
| T2 | MBR ←Memory PC←PC+1 | MBR gets instruction from memory through data bus PC gets incremented |
| T3 | IR ←MBR | IR gets instruction from MBR |
Note:
- There is no PC € PC + 1 in the first T-state.
- This is so that the PC can supply the address on the address bus through MAR in the 1st T-state. The incremented address will be placed on the address bus if PC is incremented concurrently.
Micro- operation for immediate addressing mode:
E.g : MOV R1, 25H; R1 register gets the immediate value 25H
| STATE | MICRO-OPERATION | EXPLANATION |
| T1 | MAR ←PC | PC puts address of the next instruction into MAR |
| T2 | MBR ← Memory (Instr) | MBR gets instruction from memory through data bus |
| T3 | IR ← MBR PC←PC+1 | IR gets instruction “MOV RI, 25H” from MBR PC gets incremented |
| T4 | R1 ←25H (IR) | RI register gets the value 25H from IR |
Micro-operation for register addressing register:
E.g: MOV R1, R2; R1 register gets the data from Register R2
| STATE | MICRO-OPERATION | EXPLANATION |
| T1 | MAR ← PC | PC puts address of the next instruction into MAR |
| T2 | MBR ← Memory (Instr) | MBR gets instruction from memory through data bus |
| T3 | IR←MBR PC ←PC +1 | IR gets instruction “MOV RI, R2″ from MBR PC gets incremented |
| T4 | R1←R2 | R1 register gets the value from R2 register |
Micro-operation for direct addressing mode:
E.g : MOV R1, [2000H]; R1 register gets the data from memory location 2000H
| STATE | MICRO-OPERATION | EXPLANATION |
| T1 | MAR←PC | PC puts address of the next instruction into MAR |
| T2 | MBR←Memory (Instr) | MBR gets instruction from memory through data bus |
| T3 | IR←MBR PC ←PC +1 | IR gets instruction “MOV RI, [2000H] ” from MBR PC gets incremented |
| T4 | MAR←IR (2000H) | MAR gets the address 2000H from IR |
| T5 | MBR ←Memory ([2000H]) | MBR gets contents of location 2000H from Memory. |
| T6 | R1 ←MBR ([2000H]) | Register RI gets contents of memory location 2000H from MBR |
Micro-operation for indirect addressing mode:
E.g: MOV R1, [R2]; R1 register gets the data from memory location pointed by R2
| STATE | MICRO-OPERATION | EXPLANATION |
| T1 | MAR € PC | PC puts address of the next instruction into MAR |
| T2 | MBR←Memory (Instr) | MBR gets instruction from memory through data bus |
| T3 | IR ←MBR PC←PC+1 | IR gets instruction “MOV R1, [R2]” from MBR PC gets incremented |
| T4 | MAR ←R2 | MAR gets the address R2 Register |
| T5 | MBR ←Memory ([R2]) | MBR gets contents of location pointed by R2 from Memory. |
| T6 | R1 ← MBR ([R2]) | Register R1 gets contents of memory location pointed by R2 from MBR |
Micro-operation for indirect addressing mode:
E.g.: MOV [R2], R1; R1 register stores data into memory location pointed by R2
| STATE | MICRO-OPERATION | EXPLANATION |
| T1 | MAR ←PC | PC puts address of the next instruction into MAR |
| T2 | MBR ←Memory (Instr) | MBR gets instruction from memory through data bus |
| T3 | IR ← MBR PC←PC+1 | IR gets instruction “MOV [R2], RI” from MBR PC gets incremented |
| T4 | MAR ←R2 | MAR gets the address R2 Register |
| T5 | MBR ←R1 | RI puts data into MBR to store it in the memory location pointed by R2. |
Micro-operations for implied addressing mode:
E.g.: STC; Set the Carry Flag; (CF € 1).
| STATE | MICRO-OPERATION | EXPLANATION |
| T1 | MAR ←PC | PC puts address of the next instruction into MAR |
| T2 | MBR ←Memory (Instr) | MBR gets instruction from memory through data bus |
| T3 | IR ←MBR PC←PC+1 | IR gets instruction “STC” from MBR PC gets incremented |
| T4 | CF←1 | Carry Flag in the Flag Register becomes 1 |