pipelining in computer architecture

what is pipelining

pipelining hazards / hazards of pipelining ( Use both words )

pipelining processing

pipelining architecture

pipelining stages

Fast processors are always preferable because they accomplish the tasks within less time.But what makes a processor fast?

Pipelining or also known as parallelism makes a processor faster.

PIPELINING:Overlapping different stages of instruction is referred to as pipelining.

The instruction is fetched from the memory to processor through bus.The fetched instruction is executed,while execution the bus is ideal.Thus the bus fetches the next instruction to be executed.

In non-pipelined processors each instruction is executed one after the completion of the previous instruction.Time consumed is more.

2-Stage pipelining:

In 2-stage pipelining instruction process is divided into fetching and executing stages.Fetching of next instruction takes place while the current instruction is being executed.Two instructions are being processed at any point of time.

3-Stage pipelining – ARM7/80386:

In 3 stage pipelining the whole processor is divided into 3 independent units.One is responsible for fetching.Another is responsible for decoding.One is responsible for executing.

4-Stage pipelining:

In 4-stage pipelining instruction process is divided into fetching,decode,executing and store stages.

5-Stage pipelining -PENTIUM:

In 5-stage pipelining instruction process is divided into fetching,decode,address generator,execute and store stages.

6-STAGE PIPRLINING:

NON-PIPELINED PROCESSOR:

k= No.of stages =6

N=no.of instructions=5

Total cycles=K x N = 6 x 5= 30

PIPELINED PROCESSOR:

k= No.of stages =6

N=no.of instructions=5

Total cycles=K +N-1 = 6 + 5-1= 10

• Modern processors have very deep pipelining,for example Pentium 4 has a 20 stage pipeline.

Advantages of pipelining:

• To increase the performance.Deeper the pipelining,more is the level of parallelism,and hence processor becomes more faster.

Disadvantages/pipelining hazards / hazards of pipelining/Drawbacks:

1)Data Hazard/Data Dependency 

Data hazard is caused when the destination of one instruction becomes the operand of the next instruction.

Consider two instructions I1 and I2 

Assume I1: INC [4000H]

Assume 12: MOV BL, [4000H]

Clearly in 12, BL should get the incremented value of location [4000H].

But this can only happen once I1 has completely finished execution and also written back the result

at [4000H].

In a multistage pipeline, 12 may reach the execution stage before I1 has finished storing the result at location [4000H], and hence get a wrong value of data.This is called data dependency hazard.

It is solved by inserting NOP (No operation) instructions between such data dependent instructions.

2)Control Hazard/Code Hazard:

Pipelining assumes that the program will always flow in a sequential manner.

Hence, it performs various stages of the forthcoming instructions before-hand, while the current

instruction is still being executed.

While programs are sequential most of the time, it is not always true.

Sometimes, branches do occur in programs.

In such an event, all the forthcoming instructions that have been fetched/ decoded etc have to be flushed/ discarded, and the process has to start all over again, from the branch address. This causes pipeline bubbles, which simply means time of the processor is wasted.

Consider the following set of instructions:

Start:

JMP Down

INC BL

MOV CL, DL

ADD AL, BL

….

….

….

Down:DEC CH

JMP Down is a branch instruction.

After this instruction, program should jump to the location “Down” and continue with DEC CH

Instruction.

But, in a multistage pipeline processor, the sequentially next instructions after JMP Down have

already been fetched and decoded. These instructions will now have to be discarded and fetching will

begin all over again from DEC CH. This will keep several units of the architecture idle for some time.

This is called a pipeline bubble.

The problem of branching is solved in higher processors by a method called “Branch Prediction

Algorithm”. It was introduced by the Pentium processor. It relies on the previous history of the

instruction as most programs are repetitive in nature. It then makes a prediction whether branch

will be taken or not and hence puts the correct instructions in the pipelines.

 3)Structural hazard:

Structural hazards are caused by physical constraints in the architecture like the buses. Even

In the most basic form of pipelining, we want to execute one instruction and fetch the next one. Now as long as execution only involves registers, pipelining is possible. But if execution requires to read/write data from the memory, then it will make use of the buses, which means fetching cannot take place at the same time. So the fetching unit will have to wait and hence a pipeline bubble is caused. This problem is solved in complex Harvard architecture processors, which

use separate memories and separate buses for programs and data. This means fetching and

execution can actually happen at the same time without any interference with each other.

E.g.: PIC 18 Microcontroller.