ARM 7 Instruction set

Learn about arm 7 instruction set, Conditional Branch Instructions. Compared to other RISC microcontrollers, almost all ARM 7 core instructions are conditionally executed. As conditional branches are standard instructions, ARM 7 instructions were extended by adding 4 bits at the top of the 32-bit instruction field. CLICK HERE to access complete ARM series.

As the condition field has 4 bits, there can be 16 condition values. According to the condition – instruction can be executed or skipped. As we know, conditions depend on N, Z, C, and V flags in the CPSR register.

Conditional instructions are one factor that keeps a smooth program flow through the pipeline. As we know, when the usual branch occurs, the pipeline is flushed and starts refiling from the beginning.

ARM 7 instruction set

ARM 7 instruction sets split in six main categories:

  • Branch instructions in ARM
  • Data processing instructions in ARM
  • Data transfer instructions in ARM
  • Block transfer;
  • Multiply;
  • Software interruption.

Branch Instructions in ARM

Branch instructions in ARM, allows jumping forwards and backwards up to 32MB.

There are two mainly types of branch instructions in ARM:

  • Branch jump with/without link exchange (link exchange means that current PC value is stored in R14 link register);
  • Branching with/without link exchange and instruction set exchange between ARM<->Thumb(The only recommended instruction to swap between ARM and Thumb).

Data processing ARM instruction set

Another Arm instruction set is Data processing instructions in ARM includes all Logical, adding/subtracting, testing instructions (conditional/unconditional) like AND, EOR, SUB, RSB, ADD, ADC, SBC, RSC, TST, TEQ, CMP, CMN, ORR, MOV< BIC, MVN.

For instance, compiler C code: if(z==1) R1=R2+(R3x4) should compile optimally to like

EQADDS R1, R2, R3, LSL #2

Data transfer instructions in ARM

Data transfer instructions in ARM are used to move signed/unsigned Word, half-Word, and Byte data to and from the selected register. LDR and STR mnemonics.

Block transfer instructions in ARM

instructions are used to copy multiple registers with a single instruction. Using LDM and STM instructions, it is possible to Load and Store the whole register bank or subset.

Multiply instructions are used to multiply operations. There are two subsets of operands MUL, MLA for 32bit results and MULL, MLAL for 64-bit results.

Software interrupts

These ARM instruction set are Software interrupts instruction SWI transfers execution to address in memory location 0x00000008 and changes the mode to svc. SWI instruction can also be conditional. SWI instruction has 24 unused bits that can be used for storing data or custom code, which can be decoded in svc mode. This feature is handy in embedded OS when making operating system calls.

ARM 7 Instruction set
ARM 7 Instruction set

Conditional Branch Instructions

In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction’s condition field. Thus known as conditional branc instructions. This field (bits 31:28) determines the circumstances under which an instruction is to be executed. If the state of the C, N, Z and V flags fulfills the conditions encoded by the field, the instruction is executed, otherwise it is ignored. There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instruction’s mnemonic. For example, a Branch (B in assembly language) becomes BEQ for “Branch if Equal ”, which means the Branch will only be taken if the Z flag is set. In practice, fifteen different conditions may be used: these are listed in Table 4-2: Condition code summary. The sixteenth (1111) is reserved, and must not be used. In the absence of a suffix, the condition field of most instructions is set to “Always” (suffix AL). This means the instruction will always be executed regardless of the CPSR condition codes.

Conditional Branch Instructions
ARM Instruction set | Conditional Branch Instructions

Branch Instructions and Exchange Instructions (BX)

These instructions are only executed if the condition is true. The various conditions are defined in Table 4-2: Condition code summary on page 4-5. This instruction performs a branch by copying the contents of a general register, Rn, into the program counter, PC. The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the instruction set to be exchanged. When the instruction is executed, the value of Rn[0] determines whether the instruction stream will be decoded as ARM or THUMB instructions.

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Related Blogs:

8086 – All instruction set
8051 – All instruction set

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