Bus arbitration in Computer Architecture , Daisy chain method, Polling , independent requests are described in this blog. It arises as All processors can use their local bus at once in a loosely connected system. However, only one module can be using the system bus at once. There is thus competition over the system bus. It’s known as bus controversy. It is resolved using a variety of arbitration plans with various priority systems.

Daisy Chain Method

The same line is used for bus requests by all bus masters.

 • The Bus Controller sends out the Bus Grant signal if the Bus Busy line is not active. 

 • Beginning with the nearest master, the bus grant signal is transmitted serially through every master. 

 • The Bus Busy line is activated and the Bus Master, who needs the System Bus, assumes control of the System Bus.

Advantage:

I. Simple design is an advantage.

ii. There are fewer control lines. It is also simple to add new bus masters.

Disadvantage: 

1. The bus master who is physically closest to the bus arbiter has the highest priority; this is a hard rule in the bus master hierarchy. 
2. Bus access is granted serially, which causes a propagation delay in the circuit. 
3. A device failure could render the entire system inoperable. 

Polling Procedure 

The same line is used for Bus Request by all bus masters in this instance. Here, the controller creates a master’s binary address.

 For instance, 3 address lines are required (23 = 8) to connect 8 bus masters. The controller “polls” the bus masters in response to a bus request by transmitting a series of bus master addresses on the address lines.

Eg: 000,010,100,011 etc The chosen master assumes command of the bus and activates the Bus Busy queue. 

Advantage:

 i. By adjusting the polling order, it is simple to vary the Priority.

 ii. The system does not fail if one module does.

Disadvantage:

Adding more bus masters is challenging since the circuit’s address lines are multiplied. For instance, the above circuit requires 4 address lines in order to add the 9th Bus Master. 

Independent Request 

Another type in Bus arbitration in Computer Architecture. Approach Each bus master has a separate Bus Request and Bus Grant queue here. By knowing which mastevhaS asked, the controller can give that master the bus. If there are concurrent Bus Requests, the bus is allowed based on the precedence of the masters, provided that the Bus Busy line is not activated. Encoder and decoder logic for the priority make up the Controller. 

Advantage:

 i. The Bus Arbitration happens quickly. 

ii. The speed of Bus Arbitration is unaffected by the quantity of connected devices. 

Disadvantage:

More control lines are needed (2n lines are needed for n devices). 

I/O DATA TRANSFER SCHEMES 

Transfers between processor and I/O devices can be divided into four categories based on how they are started and then completed: 

1) Programmed I/O 

2) I/O driven by interrupts 

3) DMA

 4) I/O Controlled by the processor 

MEMORY MAPPED I/O	I/O MAPPED I/O
Memory space is mapped to I/O device.	I/O space is used to map I/O devices.
Memory addresses are assigned to  I/O devices.	I/O addresses are given to I/O devices.
The processor does not distinguish between I/O and memory. similarly treats I/O devices and memory devices.	The processor distinguishes between memory and I/O devices. I/O devices are isolated.
As big as memory addresses are, I/O addresses. For instance, as memory addresses in the 8085 are 16 bits, so will the I/O addresses.	As compared to memory addresses, I/O addresses are smaller. For instance, with the 8085, I/O addresses are 8 bits but memory addresses are 16 bits.
As a result, we are able to add more I/O devices. For instance, we can access as many as 216 = 65536 I/O devices in 8085.	We can now access a small number of I/O devices thanks to this. For instance, with 8085, we are limited to 28 = 256 I/O devices.
We can move data from I/O devices	Using specific I/O instructions like IN and, we can transmit data from an I/O device.
Any CPU register can be used to transport data.	A fixed register is the sole device that can transport data. For instance, just “A” registers in 8085.
Only Read and Write are required as control signals in the system.	Memory Read, Memory Write, I/O Read, and I/O Write are the four control signals that we require.
Because memory addresses are large, address decoding takes longer.	Since I/O addresses are smaller, address decoding will go more quickly.
The cost and complexity of address decoding will increase.	Decoding addresses will be less expensive and easier.

This was all about Bus arbitration in Computer Architecture . Also read about

• DMA
• Maskable Interrupts