CPSR and SPSR in ARM
The ARM architecture supports two program status registers. The current program status register (CPSR) and the stored program status register (SPSR) are the two registers (SPSR). Click here to access to full ARM series.
The CPSR in ARM is used to monitor and control internal operations. The CPSR is a dedicated 32-bit register and resides in the register file.The CPSR is divided into four fields, each 8 bits wide: flags, status, extension, and control.The extension and status fields are currently retained for future usage in current designs. The processor mode, status, and interrupt mask bits are all included in the control field. The condition flags are stored in the flags field. Extra bits have been assigned to some ARM processor cores. The J bit in the flags field, for example, is only available on Jazelle-enabled processors that can execute 8-bit instructions. Future designs are almost certainly going to have more bits for monitoring and controlling new functions.
The CPSR (current programme status register) on ARMv6/ARMv7 keeps track of four status bits: negative (N), zero (Z), carry (C), and overflow (O) (O). These bits can be utilized to execute following instructions conditionally.
The bits are set according to the most recent ALU instruction with the unique “s” suffix. The “adds” instruction, for example, modifies the status bits, but the “add” instruction does not.
Almost all ARM instructions can have an optional condition code that affects whether or not the instruction is performed.
In other words, an instruction whose condition code is evaluated to false will not change the state of the processor, such as writing a result register to change the PC.
The “LDR” instruction, for example, will only run if the Z-bit in the CPSR is set, as it will be if the most recent computing instruction returned a zero. Read about all registers in ARM7.
Current Program Status Register | CPSR
- CPSR in ARM is used in core to monitor and control internal functions. The vacant area has been set aside for future development.
- Flags, status, extension, and control are the four fields of the CPSR, each of which is 8 bits wide.
- Status and extension fields are kept for future use in current designs.
- Several ARM processor cores include extra bits allocated to the J bit (available only on Jazelle enabled processing which executes 8-bit instructions).
The individual bits represent the following:
• N – Negative result from ALU.
• Z – Zero result from ALU.
• C – ALU operation Carry out.
• V – ALU operation oVerflowed.
• Q – cumulative saturation (also described as sticky).
• J – indicates whether the core is in Jazelle state.
• GE – used by some SIMD instructions.
• IT [7:2] – If-Then conditional execution of Thumb-2 instruction groups.
• E bit controls load/store endianness.
• A bit disables asynchronous aborts.
• I bit disables IRQ.
• F bit disables FIQ.
• T bit – indicates whether the core is in Thumb state.
• M[4:0] – specifies the processor mode
SPSR Save Program Status Register
If an IRQ request occurs while the CPU is in USER mode of operation, the processor must transition to IRQ mode of operation. After copying the CPSR to the SPSR, the CPU will run in IRQ mode. After servicing IRQ mode, the CPU should switch back to USER mode and begin normal operations. As a result, SPSR is copied back into CPSR to serve USER mode.
Conclusion
The ARM architecture supports two program status registers.
The CPSR can be accessed in all processor modes, but the SPSR can only be accessed in privileged modes.
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