DMA full form is Direct Memory Access. This is basically accessing memory directly with less to no involvement of the processor.

DMA BASED I/O 

Direct Memory Access refers to data movement between memory and I/O. Due to two factors, DMA transfers are significantly faster than processor-based transfers. 

1.Since they are hardware based, fetching and decoding instructions don’t take up any time.

 2. Data is transferred straight from memory to I/O without passing through the processor. 

We require a DMA Controller like the 8237 or 8257 in order to do a DMA transfer. It has the ability to usurp the Processor’s authority over the buses. This is how the procedure is carried out. 

1) The bus master is by default the processor. 

2) The CPU initialises the DMA transfer parameters first. 

3) The processor sets the starting address and the amount of bytes to be transferred in two registers called CAR and CWCR inside the DMAC. 

4) DMAC now checks the DREQ signal to see if the I/O device is prepared for the transfer.

 5) If DREQ=1, DMAC sends a HOLD signal to the processor asking for system bus management. 

6) Following the completion of the current machine (bus) cycle, the processor releases control of the bus.

7) The processor notifies DMAC that it is now the bus master by sending HLDA. 

8) When the transfer is about to start, DMAC sends the I/O device a DACK# signal, which is by default active low but can be altered. 

9) DMAC now sends one byte per cycle. 

10) The Address register and Count register are both decremented by 1 following each byte transfer. 

11) The Terminal Count or “0” is reached by repeating this until it reaches the desired number. 

12) The transfer is now finished. 

13) DMAC makes HOLD = 0 and hands back the system bus to the processor. 

14) The processor regains control of the bus. 

Advantage of DMA 

The speed of DMA transfers is an advantage. 

Drawback of DMA

DMAC takes over as the bus master. The bus is already being occupied for DMA, hence the processor is unable to conduct any operations during DMA cycles. Processor is still in the HOLD state. 

Difference between Interrupt Request and DMA request 

When an interrupt happens, the processor must pause the running programme, run the interrupt handler, and then move on to the next main programme instruction. As a result, the CPU must finish the current instruction before responding to an interrupt request. 

The CPU only needs to enter hold state and give up control of the system bus in response to a DMA request. When the bus arrives again, it can pick up where it left off. Because of this, the processor is not required to complete the current instruction before handling a DMA request. It only needs to complete the ongoing machine cycle. 

Therefore, machine cycles are DMA breakpoints while instruction cycles are interrupt breakpoints. 

TYPES / METHODS / TECHNIQUES OF DMA TRANSFERS 

8237 has four modes of data transfer: 

1) BLOCK TRANSFER MODE / BURST MODE.

The DMAC is configured to transfer ALL THE BYTES in this mode in a single DMA transaction. The CAR and CWCR are modified once a byte has been transmitted. ONLY when all of the bytes have been sent is the system bus brought back to the processor. Although it is the quickest type of DMA, it uses the processor for extended periods of time. 

2) SINGLE BYTE TRANSFER MODE/ CYCLE STEALING.

Once the DMAC assumes control of the bus, it will only transfer ONE BYTE before giving the bus back to the processor. DMAC will once more take the bus from the CPU when one bus cycle has been completed by it. As a result, the processor and DMAC are constantly stealing bus cycles from one another. Because it keeps the CPU running in the background, it is the most often used DMA technique. The CAR and CWCR are modified once a byte has been transmitted. 

3) DEMAND TRANSFER MODE.

 The only difference between it and Block Transfer is that the DREQ must be engaged throughout the entire DMA process. Please refer to Bharat Sir’s lecture notes for more information on this if the DREQ signal drops while the procedure is being performed. The CPU can carry on with its own tasks in the interim. The DMA procedure resumes where it left off once DREQ is high once more. This indicates that the transfer occurs when requested by the I/O device, thus the name. 

4) HIDDEN MODE / TRANSPARENT MODE.

In this mode, the DMAC does not ask the processor for bus control after the CPU has programmed all settings inside the DMAC. It instead keeps an eye on the processor. It watches for the processor to go into standby mode. ThelDMAC will take control of the bus and complete the Transfer as soon as the CPU is unoccupied. Therefore, the Transfer is completely invisible to or hidden from the processor. Thus, the name. 

To read wikipedia of DMA Click Here

Also Read RISC vs CISC.

RISC	CISC
directions with a set size	instructions with different sizes
Most instructions fetch in the same amount of time.	There are varied fetching times for instructions.
Instructions are brief and easy.	Complex and extensive instruction set.
Simple is the compiler design.	Complexity of compiler design
The total size of the programme is vast since simple instructions need many to complete a task.	Fewer instructions are needed to complete a task than would otherwise be necessary due to instructions’ increased complexity and power.
A set amount of operands is used by instructions.	Operands in instructions might vary in number.
Perfect for processors running a specific operation.	Perfect for processors carrying out a variety of tasks.
Because they are straightforward, instructions can be interpreted by a hardwired control unit.	Micro-programmed A Control Unit is necessary for instructions because they are complicated.
Since most operations are register-based, execution speed is faster.	Because most operations are memory-based, execution speed is slower.
Because the number of cycles per instruction is fixed, pipelining is improved.	Pipelining experiences additional bubbles or stalls due to the variable amount of cycles per instruction.
E.g: ARM7, PIC 18 Microcontrollers.	E.g: Intel 8085, 8086 Microprocessors.