Here in this blog, four important topics are listed: Programmed I/O , Interrupt driven I/O , Maskable Interrupt and Non Maskable Interrupt.
PROGRAMMED I/O
1) In this case, the processor completely controls the data transfer between the processor and the I/O Devices.
2) Because the transfer is carried out by a special programme, the technique is also known as programmed I/O.
3) The CPU examines the state of each I/O device on a regular basis to see if any of them needs to execute any data transfers.
4) Since polling is another name for checking a device’s status, the technique is also known as polled I/O.
5) The processor will complete the transfer with any device that is prepared for it before moving on to the next.
Advantage
It is the most straightforward and hardware-free of the four data transport techniques.
Drawback
Its primary flaw is that it consumes a significant amount of processor time to continuously verify the condition of all the devices.
INTERRUPT DRIVEN I/O
1) The transfer is not started by the processor in interrupt-driven I/O.
2) As an alternative, an I/O device must interrupt the processor in order to perform a data transfer with it.
3) An interrupt is a circumstance that forces the execution of an ISR (Interrupt Service Routine) by the processor.
4) The processor will transfer data to the I/O device during the ISR.
5) This frees the processor from having to check the status of every I/O device on a regular basis, which helps the processor save time.
6) The processor is allowed to do its own business.
7) A device will interrupt the processor whenever it needs to transfer data.
This many I/O devices are present
8) The number of I/O devices that the processor can communicate with.
9)For instance: Keyboard. The keyboard interrupts the processor when a key is pushed, rather than the CPU constantly checking to see if a key is pressed. The CPU will read the data from the keyboard’s ISR, which is a component of the keyboard driver software.
10)Consequently, interrupt-driven I/O is superior to polled (or programmed) I/O.
INTERRUPT HANDLING MECHANISM
1) The CPU completes the current instruction when an interrupt happens.
2) After then, the running programme is suspended and an ISR is run.
In order to do this, it Pushes the value of PC (the address of the subsequent instruction) into the stack.
4) The ISR is now loaded into the PC and is being executed.
5) It POPs the return address off the stack and loads it back into the PC at the conclusion of the ISR.
6) This is how the processor navigates to the program’s very next instruction.
| INTERRUPT DRIVEN I/O | POLLING (PROGRAMMED I/O) |
| Every time an I/O device has to transfer data, it interrupts the processor. | Each I/O device’s state is frequently checked (called a “poll”) by the processor to determine whether it needs to conduct a data transfer. |
| Processor saves system time since it is free to conduct its own processes. | System time is lost since the processor is constantly scanning all I/O devices. |
| To manage interruptions, more hardware is needed. E.g.:: 8259 controller for programmable interrupts. | No additional hardware is necessary. |
| increases the system’s cost and complexity. | System is simpler and less expensive. |
| Either software or hardware must be used to manage interrupt priority. | No such problem. |
| IVT, or an interrupt vector table, must be used to hold interrupt vector addresses (ISR Addresses). | No such problem. |
Types of interrupts :
1. VECTORED AND NON VECTORED INTERRUPTS:
- The ISR address is a crucial component in interrupt handling.
- An interrupt is referred to as a vectored interrupt if the ISR address is fixed. Because the processor is aware of the ISR address, such interrupts are handled more quickly. But these breaks are rigid.
- They can only service one device because they have a fixed ISR address.
- They are unable to accept interruptions from several gadgets.
- They are unable to increase the interrupt structure.
- E.g.:: The 8086 NMI interrupt has a fixed vector number of 2.
- An interrupt is referred to be non-vectored if it lacks a fixed ISR address.
- These interruptions operate more slowly.
- The interrupting device, which is often an interrupt controller like the 8259, provides the ISR address.
- But these interruptions are adaptable.
- They can take interrupts from various devices because they don’t have a defined ISR address.
- They can therefore be applied to increase the interrupt structure.
- E.g.:: 8086 INTR interrupt (can handle any vector number between 0 and 255)
2. MASKABLE INTERRUPTS AND NON MASKABLE INTERRUPTS
An interrupt that has a masking feature can be turned off. If this interrupt is disabled, the processor will simply ignore it and carry on with the main programme whenever it occurs. These interrupts are typically used to handle non-critical, low priority events like keyboard pushes that can be readily deactivated (the keypad can be locked). Such interrupts belong to this maskable interrupt and non maskable interrupts.
For instance, the 8086’s INTR interrupt is deactivated when the interrupt flag is set to 0.
An interrupt that cannot be turned off is referred to as non-maskable. The CPU will need to respond to this interrupt each time it happens. These interruptions are typically utilised to manage urgent, life-or-death situations, including the mother board overheating or a power outage.
For instance, the 8086’s NMI interrupt (which is never disabled)
3. SOFTWARE AND HARDWARE INTERRUPTS
Based on how the interruption happens, this.
A software interrupt is one that results from the writing of an instruction. Software interruptions are predictable occurrences that the programmer causes.
E.g.:: The 8086’s INT n instruction (n can range from 0 to 255)
A hardware interrupt is one that is brought on by a signal on an external pin. Unpredictable occurrences called hardware interrupts are produced by external devices.
For instance: 8086’s NMI and INTR pins
Also read about DMA, where processor is not involved in between memory and I/O communication.