Addressing Modes in ARM

The phrase addressing modes in ARM relates to the manner an instruction operand is expressed. Before the operand is actually performed, the addressing mode provides a rule for interpreting or altering the address field of the instruction. Also read about data processing instructions in arm, Register indirect addressing mode, Register indirect addressing mode

Data Processing Instruction in ARM (i.e. op1) Addressing Modes

There are two approaches to dealing with these data processing instructions in arm.
Unaltered value :The register or a value is delivered unchanged, that is, without any shift or rotation, in this addressing style, for example, I MOV R0, # 1234 H The instantaneous constant value 1234 will be moved into register R0 by this instruction.
Modified value :The provided value or register is shifted or rotated in this addressing mode. As shown below with examples, there are several shift and rotate operations that may be performed.

(1) Leftward logical shift This will move the value of a register by n bits in the direction of the most significant bits.For eg. MOV R0, R1, LSL #2
R0 will become the value of R1 shifted 2 bits once this instruction is executed.

(2) Right logical shift This shifts the value of a register by n bits to the right. MOV R0, R1, LSR R2 are several examples. R0 will have the value of R1 moved right by R2 times once this instruction is executed. R1 and R2 are unaffected.

(3) Right arithmetic shift This is identical to logical shift right, except that for arithmetic shift operations, the MSB is maintained as well as shifted, e.g. MOV R0, R1, ASR #2. R0 will have the value of R1 Arithmetic; moved right by 2 bits after this instruction is executed.

(4) Rotate to the right. This will rotate the value of a register by n bits, for example MOV R0, R1, ROR R2. R0 will have the value of R1 rotated right for R2 times once this instruction is executed.

(5) Extend right rotation This is comparable to Rotate right by one bit with the carry flag put into the MSB,.The value of register R1 will be rotated right through carry by 1 bit once this instruction is executed.

Addressing modes in ARM

To access memory, load and store instructions are utilised, as previously mentioned. The various memory access addressing modes are as follows:

(i) Register indirect addressing mode
(ii) Indirect addressing mode for relative registers
(iIi) Indirect addressing method with a base index
(iv) Scale register addressing mode as a base

As demonstrated in the examples for each addressing method, offset addressing, pre-index addressing, and post-index addressing are all available.

Register indirect addressing mode

A register is utilised in this addressing mechanism to provide the address of the memory region to be accessed. LDR R0, [R1] is an example. This instruction loads the 32-bit word at the memory location contained in register R0 into register R0. This is known as Register indirect addressing mode.

Indirect addressing mode for relative registers

 An instantaneous value applied to a register generates the memory address in this addressing style. This method of Addressing modes in ARM allows for both pre- and post-indexing.
For example, (a) LDR R0, [R1, #4]
This instruction loads the register R0 with the word at the memory regions computed by adding the constant address included in the R1 register value 4 to the memory address stored in the R1 register, e.g. (b) LDR R0, [R1, #4]! 
This is a type of addressing that comes before the index. This instruction is the same as (a) in that it sets the new address in R1,
i.e. R1 (R1 + 4). e.g. (c)’LDR, [R1], #4
This is referred to as post-index addressing. This instruction loads the word at the memory location supplied in register R1 into register R0. It will then compute the new address by multiplying R1 by 4 and storing it in R1.

Indirect addressing method with a base index

In this Addressing modes in ARM , The memory address is produced by adding the values of two registers in this addressing scheme.. For example, (a) LDR R0, [R1, R2]
Pre indexing and post indexing is also supported.
This instruction will load the word at the memory address determined by adding register R1 and register R2 into register R0.
For example, (b) LDR R0, [R1, R2]!
This is pre-index addressing.
This instruction loads the word at the memory location supplied in register R1 into register R0. The new address will then be calculated by adding the value in register R2 to register R1 and placed in R1.

Scaled register addressing mode as a base

In this Addressing modes in ARM, the memory address is produced by adding a register value to another register that is moved left in this addressing scheme. This addressing technique allows for pre-indexing and post-indexing.
For eg., (a) LDR R0, [R1, R2, LSL #2]
The word at the memory location computed by adding register leith register R2 shifted left by 2 bits will be loaded into register R0 using this command. For instance, (b) LDR RO,[R1, R2, LSL #2]!

This is an address that has been pre-indexed.

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