Interrupts in PIC Microcontroller

Interrupts in PIC Microcontroller

Interrupts are special events that when taken place, need to be handled right away. In case of a CPU which is deeply ordered, this was applied to allow emergency external events to get the attention of the CPU, emergencies like power failure, the system overheating or major failure of a subsystem in earlier days. But the concept of interrupts was recognised as very powerful, and as time went on, more and more subsystems gained the power to generate interrupts. This forced increasing complexity in interrupt structures and a need to recognise that not all interrupts were equal.

PIC16F877A Microcontroller Interrupt Structure

PIC 16F877A has the following 15 interrupt sources:

External
Timer 0
Timer 1
RB Port Change
Parallel Slave Port Read/Write
A/D Converter
USART Receive
USART Transmit
Synchronous Serial Port
CCP1 (Capture, Compare, PWM)
CCP2 (Capture, Compare, PWM)
TMR2 to PR2 Match
Comparator
EEPROM Write Operation
Bus Collision

INTCON Register in PIC

GIE: Global Interrupt Enable bit

1-Enables all unmasked interrupts
0-Disables all interrupts

PIE: Peripheral Interrupt Enable bit

1-Enables all unmasked peripheral interrupts
0-Disables all peripheral interrupts

TMR0IE: TMR0 Overflow Interrupt Enable bit

1-Enables the TMR0 interrupt
0-Disables the TMR0 interrupt

INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt

RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

TMR0IF: TMR0 Overflow Interrupt Flag bit

1-TMR0 register has overflowed (must be cleared in software)
0-TMR0 register did not overflow

INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur

RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software).
0 = None of the RB7:RB4 pins have changed state

The interrupt structure and the SFR that controls it, INTCON, are described above. It is useful to study the two in parallel, as every bit in the INTCON register appears in the structure logic diagram. Each source has an enable line (denoted by E) and a flag line (denoted by F).

Thus, the lines TOIF, INTF and so on are actually the interrupt flags, rather than the interrupt inputs themselves. All can be seen as bits in the INTCON register, with the exception of the EEPROM write complete flag and enable. Note that the external interrupt is edge triggered. The edge it responds to is controlled by the setting of the INTEDG bit of the OPTION register which has been described below.

OPTION Register in PIC

The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 Prescaler/WDT Postscaler (single assignable register known also as the Prescaler), the external INT interrupt, TMR0, and the weak pull-ups on PORTB.

RBPU: PORTB Pull-up Enable bit (This bit is not used for timers)

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values

INTEDG Interrupt Edge Select bit

1 = Interrupt on the rising edge of RB0/INT pin
0 = Interrupt on the falling edge of RB0/INT pin

T0CS: TMR0 Clock Source Select bit

1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)

T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

PS2:PS0: Prescaler Rate Select bits

Interrupt Order

When an interrupt occurs, the program stops executing and the value of the program counter is put on stack after which it moves to interrupt service vector. At the time of interrupt trigger, the flag associated with that interrupt gets saved and the GIE bit is cleared. The core registers like W, STATUS, PCLATH etc., are saved in temporary registers which allow everything to be restored when we return from the interrupt using RETFIE.