Architecture of 8086

This tutorial expalins the deep working os architecture of 8086 microprocessor diagram and step wise working architecture of 8086 microprocessor with block diagram. Architecture of 8086 microprocessor is divided into two units BIU and EU because of pipelining ( refer pipelining tutorial ).

Bus Interface Unit – BIU

This stands for bus interface unit.

This unit consists of few special purpose registers. It mainly consists of segment registers ( refer memory segmentation tutorial ) , that stores the segment addresses. 

Code Segment in 8086 ( CS )

It is known as code segment. User gives the 16-bit segment address to the CS register.

Instruction Pointer in 8086 ( IP )

This stands for instruction pointer. It is an offset address for the code segment. 
PA = ( CS x 10_H ) + IP

Using CS and IP, physical address is calculated in the address generation circuit.

Every symbol of such type, represents that it is for arithmetic operations.

Working in BIU

Programmer gives the virtual address ( segment address and Instruction pointer ) , now the code segment and IP values are converted to physical address ( actual address ) by the address generation circuit.

Then a 20-bit physical address is put on 20 address lines, then a signal is sent by the control bus to read or write the data. Then the instructions are fetched and come in a 6 byte queue.

Queue is a data structure that follows first in first out principle. This is a 6 byte queue because the size of any instruction in 8086 can be of size from 1 byte to 6 bytes.

While the EU is executing the instruction ,here instructions are fetched in this queue.

Few cases

• Let’s assume the queue is already filled about 4 bytes and the space remaining in the queue is 2 bytes but the next instruction is of 5 bytes.
  In this case a small part of the next instruction is fetched, however before execution of the previous instruction, the current 5 byte instruction will be fetched completely.

• Pipelining fails in the branch operations, if any such instruction comes, the whole queue is discarded. 

Instructions in the queue are stored in the form of opcodes.

Execution Unit in 8086 ( EU )

This is an execution unit where instruction decoding and execution takes place.

Opcodes ( which are stored in queue ) from the queue are transferred into the control unit, where decoding happens. Decoding means understanding the opcode. Once decoding is completed, the control system transmits signals to the overall processor. Now the operands are sent to ALU, and the result is stored in general purpose registers and status of the result is stored in flags.

 Operands register is for storing temporary operands, which is not accessible to the user. For example this register is used while swapping. 

Stepwise working of 8086

Converting virtual address into physical address for memory access:

The following flow shows the stepwise working of 8086, and proper architecture of 8086 diagram. User gives a virtual address, which is stored in segment registers and offset registers which are 16-bit special purpose registers. 

Once the virtual address is converted into physical address,

• physical address is put on 20 address lines.
• Control signal ( read / write ) is sent by the processor through the control  bus.
• Data is accessed from that location using data buses. 

Instruction fetching:

While the first instruction is executing, the second instruction is fetched by incrementing the IP. These instructions are stored in a queue. The instructions come in the form of opcode. 

The process of fetching the instructions, while the previous instruction is being executed is known as prefetching.

Instruction decoding:

Once the present instruction is executed in the EU, it is ready to execute the next instruction present in the 6-byte queue. 

Instruction enters the control unit after the execution of previous instruction. The control unit decodes the instruction. 

Execution:

From the control unit , operands are sent to ALU. ALU produces two results, one is normal output, other is status ( which means whether there was a carry in the output or not ). Status is stored in flag register, in upcoming tutorials.

Result saving:

After the execution is completed, the result is saved in some general purpose registers, and the target register is defined by the user.

There are four general purpose registers in the EU .

AX, BX, CX, DX. These are 16-bit registers which also can be divided into two 8-bit registers.

AX has AH, AL small registers. AH stands for higher byte of AX and similarly other registers. 

EU also has 4 offset registers ( refer memory segmentation ) .

More about flag register would be discussed in the next tutorial. 

Complete internal architecture of 8086 diagram is

Below is the architecture of 8086 microprocessor with block diagram

Also check wikipedia page of 8086.