8255 PPI

8255 PPI stands for Programmable Peripheral Interface, which means it is a programmable device used to interface I/O devices with the processor. In reality, we are not supposed to connect I/O devices directly with the data bus of the processor ,instead there should be some device to which I/O ports should be there to connect I/O devices. This article consists of architecture of 8255, working of 8255, modes in 8255 and 8255 ppi block diagram.

It has 3 8bit ports, all ports are bidirectional ( can be used as Input port or output port ) . 

8255 PPI Working

As already mentioned 8255 has 3 data ports namely Port – A ( PA ) and PB, PC. Architecture of 8255 :

1. Assuming the connected device to be an input device. Initially, the Input device seeks for permission from PPI so that it can send data. 

2. In architecture of 8255 , PPI permits Input devices to send data, only when there is no left data in 8255 which should be sent to the 8086 processor. If there is some previous data left in 8255, which is still not sent to 8086, then it doesn’t permit Input device.

3. Once 8255 permits input device, data is received and stored in temporary registers in 8255. Once 8255 holds some data, which should be sent to 8086, then it send signal to 8086.

4. Whenever 8086 is free to receive the data, then 8086 sends back a signal , after that data transmission happens between 8255 and 8086. If 8086 do not becomes free upto long time, which means 8255 has some value in it which is still not sent to 8086, so 8255 does not permit the Input device to send any data because the existing data will be overwritten. 

All the signal in the above diagrams represented using red curved arrow are known as handshake signals. This process of data transmission is known as handshaking. 

Architecture of 8255

Note : Don’t get confused by seeing the architecture of 8255, go through the complete article and any queries are welcomed in the comment section. 

 Left part of 8255 shows the interfacing of it with the 8086 microprocessor. 

• Data bus buffer is connected to 8086 ( 8-bit data bus ). 
• Block below it, Control block is used for control over PPI.

Pin Name	Purpose
RD bar	It is an active low signal. when it is 0, it means 8086 is reading data from 8255 through a data buffer, which was sent by an input device.
WR bar	It is also an active low signal. When it is activated , it means 8086 is sending data to 8255 through the data buffer block.
A1 and A0	As there are 3 ports to 8255 and one control word. Whenever data enters 8255 from 8086 processor. It can go to PA , PB, PC or CW. To define target location we need two pins. In 8086, A1 is connected to A2 and A0 is connected to A1 A1A0Target00PA01PB10PC11CW
Reset	This pin is used to reset the 8255 device.
CS bar	This pin is chip select. It is used to select the device.

Three ports of PPI are divided into 4 parts . Port-C is divided into two ports of 4 bits each. PC lower ( PCL ) and PC upper( PCU ). Physically there are 3 ports only. This 3rd port is divided logically.

Two ports PA and PCU are under group-A control. And other 2 ports are under control of group-B . 

Why is the PC ( Port – C ) divided into two parts ?

As already discussed about handshaking, we require some lines for handshaking. We need 3 lines for handshaking for 1 port. Basically 8255 can be operated in 3 modes. 

		PA	PB	PCL	PCU
Mode 0	SImple	Works as port	Works as port	Works as port	Works as port
Mode 1	Handshaking	Works as port	Works as port	Used for handshaking in PB	Used for handshaking in PA
Mode 2	BidirectionalHandshaking	Works as port in Mode	Works in mode – 0 or mode – 1	Used for handshaking in PB	Used for handshaking in PA

In the PPI of architecture of 8255 , data is sent to ports and commands are sent to the control group. Commands are sent to initialize the 8255, hence it is a programmable device, which means we can set it according to our requirements. Basically there are two types of commands I/O commands and BSR commands. 

I/O commands:

If the D7 = 1, then it is I/O command or else it BSR command.  (( Architecture of 8255 ))

D6 and D5 are for mode selection of port A
D4 is to determine whether port A is input port or output port.
D3 is used for determine whether port C – upper is input port or output port. 

D2 is used to select mode of Port B
D1 is to determine whether port B is input port or output port.

D3 is used for determine whether port C – lower is input port or output port. 

If this command is 92H which mean 10010010

PA	Mode 0	Input port
PB	Mode 0	Input port
PC	Mode 0	Output port

BSR command

In the process of handshaking of architecture of 8255 , 6 lines out of 8 lines of PC are utilized in handshaking, remaining two lines can be used for attaching bit addressable I/O devices. Such as an Air Conditioner can be attached to one of these lines. BSR stands for Bit Set Reset command. 

Here D7 = 0 for BSR command.
D6, D5, D4 do not care pins.
D3 , D2, D1 are used to select pins on the PC.
D0 is for set or reset, for the selected pin. 

This was all about architecture of 8255 . Also read
8259 Architecture
Complete 8086 series
Wikipedia page of 8255