ARM Registers 

Basically there are two types of registers – General purpose registers and Special purpose registers. General-purpose registers hold either data or an address. The letter r is prefixed to the register number to identify them. For example, the label r4 is assigned to register 4. Figure  depicts the active registers that are available in user mode, which is a protected state that is often utilized for running programmes. There are seven various modes that the CPU may work in, which we shall go through momentarily. The registers in this example are all 32 bits in size. Up to 18 active registers are available: 16 data registers and 2 processor status registers. The data registers are labeled r0 through r15 by the programmer. The ARM processor contains three registers: r13, r14, and r15, each of which is allocated to a specific duty or unique function. To distinguish them from the other registers, they are typically given separate labels. The coloured registers indicate which special-purpose registers have been allocated. Click here to access complete ARM series.

• Register 13 is traditionally used as the stack pointer (SP) and stores the head of the stack in the current processor mode. 
• Register r14 is called the link register (LR) and is where the core puts the return address whenever it calls a subroutine. 
• Register 15 is the program counter (PC) and contains the address of the next instruction to be fetched by the processor.

Depending upon the context, registers r13 and r14 can also be used as general-purpose registers, which can be particularly useful since these registers are banked during a processor mode change.While the CPU is running any type of operating system, it is risky to utilize r13 as a general register since operating systems frequently believe that r13 always refers to a valid stack frame. The registers r0 to r13 are orthogonal in ARM state, which means that any instruction that can be applied to r0 may also be applied to any of the other registers. There are, however, instructions that treat r14 and r15 differently. There are two program status registers: cpsr and spsr, in addition to the 16 data registers (the current and saved program status registers, respectively). The register file includes all of the registers that a programmer has access to. The current mode of the computer determines which registers are visible to the programmer.

Few of these registers are actually banked and different registers are available for different processor modes. The following are special functions registers in ARM.

SP ( Stack Pointer )

• The stack pointer, often known as the SP register, is located in register r13.
• Each exception mode has its own version of r13, pointing to a stack specialised to that mode.
• Temporary values are stored in the stack.
• This was the purpose of SP ARM registers

LR ( The link register )

• The Link register, also known as register r14, is used to store the subroutine’s return address. 
• When an exception occurs, the version of r14 in the exception mode is set to the address after the instruction is executed.
•  SPSR is a copy of the CPSR just before an exception has occurred.

PC ( Program Counter )

• The Program Counter, sometimes known as the PC, is located in register r15.
• It’s used to determine which instruction will be executed next.
• The PC is referred to as an instruction pointer because it stores the address of the next instruction.

CPSR ( Current Processor Status Register ) – Important ARM Registers

This is a very important and one among most used ARM registers. This is similar to flag register in 8051.

•Current processor status register (CPSR) contains the current status of the processor.
•This includes various conditional code flags, Interrupt Status Processor mode and other status and control information.
•The exception modes also have a saved processor status register (SPSR), that is used to preserve the value of CPSR when the associated exception occurs.
•Because the User and System modes are not exception modes,  there is no SPSR available.

SPSR ( Saved Processor Status Register )

In the exception modes there is an additional Saved  Processor Status register (SPSR) which holds information on the processor’s state before the system changed into this mode i.e. the processor status just before an exception.

This was all about ARM registers. For detailed information – Click Here