Interrupts in 8086
Interrupt
interrupts in 8086 is a special condition that arises while the microprocessor is executing the main program. Then the microprocessor stops where it is executing in the program and goes to the Interrupt service routine ( ISR is the another code ) , the microprocessor executes the ISR and completes it and then continues the main program. This is similar to call branching. The called function is known as Subroutine in the case of call branching, Here it is Interrupt service routine( ISR ). In the call branching, to return to the main program RET command is given at the end of the subroutine, here IRET is the command to return to the main program.
Eg: Playing a game in mobile phone ( Processor is running main program i.e. game )
A call comes, then the processor pop ups the call ( here call is an interrupt ), then processor goes to ISR ( here
ISR is call )
How many interrupts in 8086:
There are 256 interrupts in 8086 microprocessor, Each interrupt is defined as
INT n
Where n ranges from [ 0 , 255 ]
Basically 8086 executes the main program which is present in the code segment and interrupt code is present in other segments, as said there are 256 interrupts which means there are 256 codes present somewhere in the memory. So interrupt is an intersegment branching. After execution of ISR, processor should come back to the next location where it left for ISR, it means after executing ISR, processor should come and continue from 55H .
How Processor gets return address:
If the return address is written in ISR:
In the above figure processor left the main program at 54H , and went to ISR, if the last instruction of ISR was JMP 55H.
Let’s consider the same ISR in another case, if the processor leaves the main program at 58H and goes to ISR. At last ISR sends the processor to 55H , which is completely wrong.
Correct:
So the return address is not given anywhere in the ISR or main program. Return address is stored in stack while going to ISR, and the RA is pushed whenever the IRET command appears.
As it is intersegment branch, IP and CS both would be changing, So while going to ISR, both IP and CS would be pushed in stack and while returning both are popped. IP and CS are pushed into stack by the rule, lower byte lower address.
Steps followed :
- In the above diagram, the program is sequentially fetched upto location 54H.
- While 8086 is executing 54th instruction ( INT n ), 55th instruction and location are already fetched because of pipelining. Once the processor executes 54th instruction which is INT n instruction, 55th location is pushed into stack.
- Then IP ←ISR top address.
- Now the ISR is executed completely in a sequential manner.
- Once completed, the processor gets the IRET command.
- So now the stack is popped, and that value is given to the IP and CS.
- So IP←55, and continues.
Inside the interrupt( ISR ), internally the number of pushes in the stack should be the number of pops, else the return address would not be given correctly to the IP and CS.
Why is stack used to store the return address?
When there are nested interrupts ( an interrupt inside another interrupt ), all the return addresses of successive main programs would be pushed into the stack, and while returning respective return addresses are popped.
8086 interrupt vector table:
The Interrupt Vector ( IVT ) table in 8086, is the place where the address of all 256 interrupts is stored. This vector table is itself in the 8086 memory ( memory attached to 8086 )
INT n ; here n ranges from 0 to 255
Whenever the processor tackles this instruction, it goes to the vector table. For example INT 3 is the command, it goes to IVT, and gets the location of INT 3 interrupt from interrupt vector table ( IVT ) and then it goes to location of INT 3 which is ISR.
If processor gets interrupt it goes two times to memory
- To get the address of interrupt from interrupt vector table.
- And then goes to the location of ISR for execution of ISR.
In 8086, IVT location is 00000H . Each location can store 8-bits , so 4 locations in IVT are used to store one interrupt’s address, 2 locations for CS and 2 locations for IP addresses.
As there are 256 interrupts and each interrupt’s address requires 4 locations, 256×4 = 1024 locations are present in IVT. Size of the IVT is 1kb.
To access any address of nth interrupt, a generalized formula is
To access IPL address : ( n x 4 )
To access IPH address : ( n x 4 ) + 1
To access CSL address : ( n x 4 ) + 2
To access CSH address : ( n x 4 ) + 3
Few more cases:
- Processor is executing the main program with TF = 1 ( refer flag register )
- At the moment suddenly an interrupt occurs
- So TF=1 already, if the processor executes ISR considering TF=1 , it takes long time and it is undesirable too.
- Not only TF, If CF = 1, until interrupt and in ISR due to some reasons CF became 0. With CF=0, if processor proceeds in main program, it causes error.
To avoid such cases, while going to ISR IF and TF are made 0 as well as flag register is also pushed into stack
And while returning flag register is also popped with IP and CS.
In normal branching operations ( non – interrupts ) the flag register is not pushed into the stack.
Types of interrupts:
There are two types of interrupts
- Software interrupts or user defined interrupts
- Hardware interrupts ( 2 pins of 8086 )
External Signal (Hardware Interrupts):
These interrupts occur as signals on the external pins of the µP. 8086 has two pins to accept hardware interrupts, NMI and INTR.
Special instructions (Software Interrupts):
These interrupts are caused by writing the software interrupt instruction INTn where “n” can be any value from 0 to 255 (00H to FFH). Hence all 256 interrupts can be invoked by software.
Condition Produced by the Program (Internally Generated Interrupts):
8086 is interrupted when some special conditions occur while executing certain instructions in the program. Eg: An error in division automatically causes the INT 0 interrupt
256 interrupts are divided as
1. Dedicated interrupts
2. Reserved interrupts
3. User defined interrupts
DEDICATED INTERRUPTS (INT 0 … INT 4)
1)INT 0 (Divide Error) :
This interrupt occurs whenever there is division error i.e. when the result of a division is too large to be stored. This condition normally occurs when the divisor is very small as compared to the dividend or the divisor is zero. Its ISR address is stored at location 0 x 4 = 00000H in the IVT.
2) INT 1 (Single Step):
The µP executes this interrupt after every instruction if the TF is set. It puts µP in Single Stepping Mode i.e. the µP pauses after executing every instruction. This is very useful during debugging. Its ISR address is stored at location 1 x 4 = 00004H in the IVT.
3) INT 2 (Non Maskable Interrupt):
The µP executes this ISR in response to an interrupt on the NMI line. Its ISR address is stored at location 2 x 4 = 00008H in the IVT.
4) INT 3 (Breakpoint Interrupt) This interrupt is used to cause Breakpoints in the program. It is caused by writing the instruction INT 03H or simply INT. It is useful in debugging large programs where Single Stepping is inefficient. Its ISR is used to display the contents of all registers on the screen. Its ISR address is stored at location 3 x 4 = 0000CH in the IVT.
5) INT 4 (Overflow Interrupt):
This interrupt occurs if the Overflow Flag is set AND the µP executes the INTO instruction (Interrupt on overflow). It is used to detect overflow error in signed arithmetic operations. Its ISR address is stored at location 4 x 4 = 00010H in the IVT. Please Note: INT 0 … INT 4 are called as dedicated interrupts as these interrupts are dedicated for the above-mentioned special conditions.
RESERVED INTERRUPTS OF 8086
INT 5 … INT 31
These levels are reserved by INTEL to be used in higher processors like 80386, Pentium etc. They
are not available to the user
USER DEFINED INTERRUPTS IN 8086
INT 32 … INT 255
These are user defined, software interrupts.
ISRs for these interrupts are written by the users to service various user defined conditions.
These interrupts are invoked by writing the instruction INT n.
Its ISR address is obtained by the µP from location n x 4 in the IVT.
HARDWARE INTERRUPTS
1) NMI (Non Maskable Interrupt)
This is a non-maskable, edge triggered, high priority interrupt. On receiving an interrupt on NMI line, the µP executes INT 2. µP obtains the ISR address from location 2 x 4 = 00008H from the IVT. It reads 4 locations starting from this address to get the values for IP and CS, to execute the ISR. INTR This is a maskable, level triggered, low priority interrupt. On receiving an interrupt on INTR line, the µP executes2 INTA pulses.
1st INTA pulse — the interrupting device calculates (prepares to send) the vector number.
2nd INTA pulse — the interrupting device sends the vector number “N” to the µP. Now µP multiplies N x 4 and goes to the corresponding location in the IVT to obtain the ISR address. INTR is a maskable interrupt. It is masked by making IF = 0 by software through CLI instruction. It is unmasked by making IF = 1 by software through STI instruction.
Overall when processor goes to ISR
- 8086 would push flag register into stack FH and FL
- IF and TF flag are cleared
- CS address is pushed, CSH and CSL
- IP address is pushed , IPH first and then IPL
- New IP and CS are loaded from IVT ( interrupt vector table )
While returning to RA, and also response to IRET instruction:
- First IP is stored ( stack is last in first out )
- Then CS is popped
- And at last flag register is popped back.