Maximum mode of 8086
Maximum mode in 8086 refers to the situation when 8086 is not only the processor to compute, with 8086 there are few other processors that are interfaced with it in order to boost up the performance. 8087 , 8089 are some of the processors whose interfacing with 8086 would be explained in upcoming tutorials.
In this tutorial , maximum mode configuration in 8086 is explained in detail. Whenever 8086 is shifted from minimum mode to maximum mode many pins get changed. Few pins in maximum mode does not support in minimum mode and vice versa.
For applications of pins in minimum mode refer to the minimum mode of 8086 tutorial. Characteristics of these 8 changed pins in maximum mode are
RQ’/GT0’ :
Here RQ’ refers to the RQ bar ( active low signal ). As known that in maximum mode, there are multiple processors who work together. In this case all the processors cannot be BUS MASTERs , By default 8086 is the bus master. If some other processor wants to become bus master then it sends a request( RQ’ ), then 8086 grants( GT’ ) the request. Once the other processor is done with the job it sends to release signal , by which 8086 becomes bus master again.
In these three steps bus control is given and taken back. So there are two such pins so that two other processors can be interfaced with 8086. If both the pins send simultaneously requests for bus control access, priority would be considered. GT0’ is more prior than GT1’.
LOCK’ :
There are two types of cycles , machine cycle and instruction cycle.
Instruction cycle:
This is a complete instruction in which it is fetched, decoded and executed. Instruction cycle contains a single/multiple machine cycle.
Machine cycle:
This cycle consists of a machine signal. Machine signals such as memory read, memory write such signals known as machine signals. Each machine cycle consists of 4 T stages ( refer timing diagram in previous tutorial )
So there are two things that can affect the processor while it is executing something. Those are interrupts and bus master requests. Whenever an interrupt occurs, processors completes the present instruction and then go to ISR ( refer interrupts ). And whenever a bus master request occurs, 8086 completes the machine cycle and loses control, whenever the bus control comes back, it continues with the next machine cycle.
LOCK’ is a signal that doesnt give the processor to grant.
LOCK MOV BX, [ 2000H ]
This is an instruction given, when users don’t want to lose bus control during this instruction cycle. And when LOCK’ = 0 ( as it is an active low signal ) main processor sends a signal that bus control will not be released.
S0’ S1’ and S2’
Let’s assume there are 3 processors that are interfaced with each other to work. By default bus master is 8086 and later according to requirements other processors can be bus masters. So there should be bus lines between each processor and each element in memory, IO ports, by which complexity would become very high. But this is wrong.
In maximum mode of 8086, no processor produces control signals.
There is a device 8288 which takes a signal from the bus master and generates a control signal.
Whichever processor is the bus master sends a signal to 8288 bus controller using the S0’ , S1’ and S2’ pins. These 3 signals are known as status signals.
| S2’ | S1’ | S0’ | Signal generated |
| 0 | 0 | 0 | INTA |
| 0 | 0 | 1 | IO Read |
| 0 | 1 | 0 | IO Write and advanced IO write |
| 0 | 1 | 1 | Halt ( no signal ) |
| 1 | 0 | 0 | Instruction fetch |
| 1 | 0 | 1 | Mem Read |
| 1 | 1 | 0 | Mem write and advanced mem write |
| 1 | 1 | 1 | Idle |
Maximum mode of 8086 Block diagram
If compared to the minimum mode block diagram all the ICs are the same, there is only one change that is 8288 bus controller.
Control signals produced from 8288:
- MRDC stands for memory read command.
- MWTC stands for memory write command.
- AMWTC stands for advanced memory write command. In normal write , write signal is activated in 3rd T stage , in advanced write it is activated in 2nd stage only ( refer timing diagram )
- IORC stands for Input Output read command.
- IOWC stands for input output write command.
- AIOWC stands for advanced input and output.
- INTA is a normal physical pin in minimum mode but here it is generated by 8288.
In maximum mode control signals are generated by 8288 bus controllers but decided by bus master ( microprocessor by Status signals ( S0….. ) ) .
How ALE is generated from 8288 bus controller :
Status signals are generated by the bus master.
Then control signals are generated by the bus controller.
According to the control signal, ALE is decided.
If it is a memory read signal, first T is the address line and then for all other T it is data. So to perfectly synchronize the same T value the same clock frequency is given to 8288 bus controller.
difference between minimum and maximum mode of 8086:
| Minimum mode of 8086 | Maximum mode of 8086 |
| MN/MX’ = 1 | MN/MX’ = 0 |
| ALE is generated by 8086 | ALE is generated by 8288 |
| T and OE’ are received from 8086 | T and OE’ are received from 8288 |
| Control signal are generated by 8086 through 74138 decoder | Control signals are generated from 8288 |
| Bus request is done using HOLD, HLDA | Bus request through RQ/GT |
| Clock frequency is provided only to processor | Clk frequency is provided to 8288 also |
| Only one processor is used | Multiple processors are used |