PSW of 8051 microcontroller

In this blog, PSW of 8051 microcontroller would be discussed. To access complete series of 8051 click here.
In the last tutorial, the architecture of 8051 was explained. In this tutorial one part of architecture PSW( program status word ) also known as Flag register of 8051 microcontrollers. 
Flag register in 8051 microcontroller is a 8-bit register and it is bit addressable ( refer previous tutorials for what is bit addressable ) . 

CY:

This is known as carry flag. This says whether there is a carry out of MSB or not. 

E.g: 1000 1101 

1011 1001 Let’s add both bytes

= 0011  0110 There is a carry out of MSB. Therefore in this case CY=1.

AC:

This flag stands for an auxiliary carry. It is given as 1 whenever there is a carry from LN to HN. LN and HN stands for lower nibble and higher nibble. As byte stands for 8 bits, similarly nibble stands for 4 bits. Lower nibble is 0-3 bits and higher nibble is 4-7 bits. 

If seen in the above example there was a carry from 3rd bit to 4th bit. So in the above case AC=1.

PARITY:

If there are even number of 1s in the result then the parity will be one, and if there are odd number of 1s then , parity=1

 Eg= 1010 1101 , here there are 5 ones, therefore parity =1

X:

This is a don’t care flag. It has nothing to do with.

OVR:

This is an overflow flag. 

There are two types numbers

• Signed
• Unsigned 

Unsigned:

These is another flag in PSW of 8051 microcontroller. This is a 8 bit positive number which ranges from 0 to 255. In hexadecimal it’s range is from 00 to FF. In the OVR flag, it has nothing to do with unsigned numbers. Only signed numbers are considered in the OVR flag.

Signed:

  This is also a 8-bit number which is equally distributed among +ve and -ve numbers. By considering MSB , it is decided whether it is a positive or negative number. If MSB=1 , it is a negative number or else a positive number.

Eg: 1011 0011 is -ve 

      0111 1001 is +ve

So it’s positive range is from 0 to 127 [ 00 to 7F (in hexadecimal ) ], it consists of 128 +ve values.

It also has 128 negative numbers ranging from -1 to -128 [ -01 to -80 ( in hexadecimal ) ].

Whenever a negative number is saved, it is saved as it’s  2’s complement. To access the number we have to make its 2’s complement again. A number is considered as negative whenever its MSB is 1, and its 2’s complement is the actual negative number.

For eg: 1011 0011

It is a negative number and its 2’s complement is 0100 1101, which is equivalent

to 4D ( hexadecimal ) . so it is -4D_H.

So there is a well defined limit for signed numbers ( 00 to 7F and -01 to 80 ) in PSW of 8051. If the result or operands exceeds the limit, it is known as overflow. If there is overflow, then the MSB would show incorrect values, if there is overflow then

MSB = 1 , then it is +ve number

MSB = 0 , then it is -ve number. This is the reverse with the original case. 

How does the processor comes to know about overflow ?

XOR operation is performed on C₆ and C₇ carry. C₀ is carried from 0th bit to 1st bit and so on. If the XOR operation gives output as 1, then the operation is going out of the limit.

F0 :

This is a user defined bit flag, where users can store any data.

RS₁ and RS₀ :

All the bit flags in PSW of 8051 microcontroller are named as PSW.0, PSW.1 ……. PSW.7 .
Internal RAM of 8051 is 128 bytes out of which 32 bytes are stored in registers( 8085, 8086 has 7,8 registers only ). These all 32 registers are divided into 4 banks, each bank has 8 registers starting from R₀ to R₇. 

Let’s assume there is an operation that should be performed on R₁, then how it decides from which bank the register is selected?

This is performed based on banks

RS1	RS0	Bank
0	0	Bank 0
0	1	Bank 1
1	0	Bank 2
1	1	Bank 3

By setting the values of RS₁ and RS₀ , we can select the register.

SETB PSW.3 

CLR PSW.4

This instruction stands for RS₁ = 1 , and RS₀ = 0, which means bank 2.

Why are registers divided into 4 banks, instead of 32 separate locations??

If every register has 32 unique addresses then each instruction requires 32 opcodes( one opcode for one unique address ), Therefore for one instruction it consumes 32 opcodes and there are only 256 opcodes and there are 111+ instructions ( add, sub, move, OR…… ) , in this way it would require ( 32 x 111 = 3552 opcodes ). So these registers are divided into 4 banks , so that only 8 opcodes are used instead of 32 opcodes. 

E.g: Let’s make an arithmetic operation and analyze all the flag values. 

In the second example, a signed overflow event had occurred, even though MSB=1, it is a positive number as in overflow condition MSB gives the opposite sign. This was all about flag register or PSW of 8051 microcontroller.

In the upcoming tutorial we would learn about memory organisation

Also read CPSR ( Sort of Flag register in ARM )

Also read flag register of 8086 microprocessor

To understand more about signed and unsigned numbers visit this wikipedia page.